(1) Field of the Invention
The present invention relates to a process for fabricating read only memory, (ROM), devices, and more specifically to a semiconductor fabrication process designed to create ROM memory cell arrays with a concave channel region.
(2) Description of Prior Art
The semiconductor industry is continually striving to increase chip performance while still maintaining the fabrication cost of the specific semiconductor chip. These objectives are being successfully addressed by the trend to micro-miniaturazation, or the ability to create semiconductor devices, with sub-micron features. This has been accomplished by advances in specific semiconductor fabrication disciplines, such as photolithography and reactive ion etching, (RIE). For example advanced exposure cameras, as well as the development of more sensitive photoresist materials, have allowed sub-micron features to be routinely created in photoresist layers. In addition the development of advanced dry etching apparatus and processes, have in turn resulted in the successful transfer of the sub-micron images in photoresist layers, to underlying materials, used in the fabrication of advanced semiconductor devices.
The read only memory, (ROM), technology has benefitted by use of micro-miniaturazation. The density of ROM memory arrays, consisting of individual ROM cells, has been increasing due to the ability to create and successfully utilize ROM devices with sub-micron features. The smaller ROM cells result in performance increases, due to decreases in parasitic capacitances, as well as decreases in cell resistances. In addition the smaller ROM cells result in smaller chips, therefore allowing more chips to be obtained from a specific size semiconductor substrate, thus reducing the fabrication cost of a specific chip. However the use of smaller ROM devices also offers specific reliability and yield issues, not encountered with larger dimension ROM counterparts. For example, the ability to create polysilicon gate structures, with sub-micron features, allows narrow channel lengths to be achieved. However the narrow channel lengths increase the reliability risk in terms of hot carrier effects. In addition the short channel effects, and punchthrough leakages, negatively influence yield.
This invention will describe a process for creating ROM devices, benefitting from the use of sub-micron features, but minimizing the risk of reliability and yield problems, encountered with narrow channel lengths. This is achieved via use of a flat ROM device, fabricated with ROM memory array cells featuring a concave channel. The use of the concave channel increases the channel length of a specific ROM cell, thus minimizing the yield and reliability concerns of narrower channels, while still not increasing the size of the specific ROM cell. Therefore this concept allows increased ROM densities, as well as minimized reliability and yield risks, to be obtained.
The present invention will describe a process for forming concave channels, for ROM devices, using the growth and subsequent removal of a field oxide region. A self-aligned bit line structure, self-aligned using the field oxide as a mask, is also a key feature of this invention. Hsu, in U.S. Pat. No. 5,448,094, describes a process of forming concave channel, metal oxide semiconductor, (MOS), transistors, however Hsu does not describe a process in which a self-aligned bit line is formed in combination with the concave channel structure. In addition, Arai, in U.S. Pat. No. 5,300,804, and Aoki, in U.S. Pat. No. 5,214,303, both describe forming ROM devices, created with flat channels, thus not benefitting from the concave channel concept, in terms of increased density and reduced reliability risk.